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Creators/Authors contains: "Nikolić, Borivoje"

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  1. ; ; ; ; ; ; ; (, IEEE Symposium on VLSI Technology and Circuits)
    Free, publicly-accessible full text available June 8, 2026
  2. ; ; ; ; ; ; ; (, IEEE)
    Free, publicly-accessible full text available June 8, 2026
  3. ; ; ; ; ; ; ; ; ; (, IEEE Symposium on VLSI Technology and Circuits)
    Free, publicly-accessible full text available June 8, 2026
  4. ; ; ; ; ; ; ; ; ; (, IEEE)
    Free, publicly-accessible full text available June 8, 2026
  5. ; (, IEEE Transactions on Circuits and Systems I: Regular Papers)
    NA (Ed.)
    Clock generation for high-speed wireline receivers must provide multiple clock phases with high-resolution rotation. To address this, an 8-phase 17 GHz clock generation circuit with built-in 6b rotation is presented. Multi-phase injection is used to perform reference-side phase rotation to efficiently generate and rotate eight clock phases. The injection method is analyzed with a model to study the introduced nonlinearity, and the effect of the injection strength is discussed. Designed by using BAG3++ for layout-aware design optimization, the proposed circuit achieves 98 fs RMS jitter and a measured DNLpp and INLpp of 1.26 and 4.05 LSB respectively, while consuming 33 mW. 
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    Free, publicly-accessible full text available January 1, 2026
  6. ; (, IEEE)
    A high frequency multi-phase clock generator circuit with a 6b phase rotator is presented for multi-phase wireline receivers. Multi-phase injection is used to efficiently generate and rotate 8 clock phases. Unlike prior rotator-based work, this work does not use time modulation, reducing the resulting deterministic jitter. A model is presented to study the nonlinearity introduced by the technique. The proposed 17 GHz circuit was implemented in the Intel 16 process and consumes 33 mW. The measured RMS jitter is $$\mathbf{9 8} \mathrm{fs}$$, and the measured DNLpp and INLpp are 1.26 and 4.05 LSB respectively. 
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    Full Text Available 
  7. ; ; ; ; ; ; ; ; ; ; et al (, IEEE European Solid-State Electronics Research Conference)
    Free, publicly-accessible full text available September 11, 2026
  8. ; ; ; ; ; (, ACM)
    Full Text Available 
  9. ; ; ; ; ; ; ; ; ; ; et al (, ACM/IEEE International Symposium on Computer Architecture (ISCA 2024))
    Accepted Manuscript Full Text Available
  10. ; ; ; ; ; (, ACM)
    Full Text Available